On completion of the course, the student should be able to:
account for the syntax and behaviour of the VHDL language
use modern development tools to design complex digital circuits
simulate and make a synthesis of extensive designs in so called "Field Programmable Gate Array" (FPGA:er).
Introduction: Overview of different design styles and abstraction methods. VHDL: The program language aspects for modelling and specification. The abstraction levels of the VHDL language. Components. Instantiation. Parallel expressions (if, case wait and loops). Functions and Procedures. Design tools: From simple VHDL editors to graphical editors, simulators and tools for synthesis of VHDL descriptions for FPGA circuits. Laboratory work: Related to basic components that are used for example in so called embedded systems.
Projects: A relatively extensive project in simulation and synthesis to achieve a non-trivial (industry relevant) design in a FPGA. How completed design blocks (so called IPs) can be used to achieve extensive circuit solutions in FPGAs and how to put together a so-called System On a Programmable Chip where an advanced processor is put together and is tested using the C programming language.
Lectures, lab-exercises and a project.
Project Work with report and individual review in examination form . Active participation during the scheduled hours. Optional written examination.
The reading list is missing. For further information, please contact the responsible department.