Accelerating Systems with Programmable Logic Components 2019/2020 (10 credits)

Spring 2020, 67 %, Campus

Start date: 23 March 2020

End date: 7 June 2020

Application Deadline: 15 October 2019

Enrolment Code: UU-61207 Application

Language of Instruction: English

Location: Uppsala

Selection: Higher education credits in science and engineering (maximum 240 credits)

Entry Requirements: 120 credits including Computer Architecture, a basic course in digital circuits (especially state machines) and a basic course in programming.
English language proficiency that corresponds to English studies at upper secondary (high school) level in Sweden ("English 6").

Fees:

If you are not a citizen of a European Union (EU) or European Economic Area (EEA) country, or Switzerland, you are required to pay application or tuition fees. Formal exchange students will be exempted from tuition fees, as well as the application fee. Read more about fees.

Application Fee: SEK 900

Tuition fee, first semester: SEK 24167

Tuition fee, total: SEK 24167

About the course:

On completion of the course, you should be able to:

  • define complex digital circuits using hardware description languages such as VHDL or Verilog
  • test, debug, and verify digital designs using test benches and simulation tools
  • integrate custom programmable logic components with processor-based systems
  • analyse power and performance of accelerating key system components
  • demonstrate how a processor interacts with an accelerator through software
Content
  • Syntax and semantics of hardware description languages, and their use to define digital systems.
  • Design and implementation of test benches and the use of simulation-based and on-chip debugging facilities for verifying system designs.
  • Parallelisation of key algorithms for higher throughput and lower latency.
  • Integration of hardware accelerators at the system- and software-levels.
  • Overview of different design styles and abstraction methods.
  • An extensive project in simulation and synthesis, designing a realistic accelerator for a system on chip processor system. 

More information

Contact

Department of Information Technology

ITC, hus 1, 2 och 4, Lägerhyddsvägen 2

Box 337, 751 05 UPPSALA

Fax: 018-511925

E-mail: info@it.uu.se