Half time seminar - Rashid Aligholipour: "Beyond Monolithic: Challenges, Frameworks, and Insights for Chiplet-Based Multi-Core"

Welcome to a haf time seminar presented by Rashid Aligholipour.

Keywords: Chiplet, PHY-link, multicore architectures To confront the increasing necessity for computational power, the transition toward larger and more powerful chips has become inevitable. Initially, larger chips appear to be a viable solution; however, challenges such as thermal limitations, testing and validation costs, lower yield ratios, and reticle size constraints have shifted designers' preferences toward alternative paradigms, such as chiplet architectures, rather than relying solely on monolithic chips. Chiplets offer a promising solution to meet the significant demand for computation at a reasonable additional cost and are better aligned with practical needs. Nevertheless, chiplets present various obstacles.

Firstly, the interconnection network (i.e., interposers and UCIe) between chiplets is often lengthy and slow, which affects the performance of certain applications, such as graph programs that exhibit high last-level cache miss rates (LLC MPKI).

Secondly, the absence of suitable simulators for modeling chiplet interconnection networks, including SerDes, modulation, and physical layer (PHY) components, leads to traditional simulators becoming imprecise when applied to these new paradigms. In this seminar, we will investigate these two issues in depth and outline strategies to alleviate the associated challenges.

The seminar is open to all and will be held in English.