Seminar: Understanding and Enhancing Electrical Transport in Graphene Heterostructures and Interfaces

The two-dimensional (2D) crystal graphene is at the forefront of material development for 2D electronic, spintronic, and neuromorphic devices. Despite over a decade of research, questions regarding its stability, interface complexities, and practical application viability persist. A deeper understanding of contact interfaces, charge traps, and scattering mechanisms could significantly improve electronic and spintronic devices. Additionally, the stability of graphene and its interfaces under high currents is critical for developing high-performance, spin current-based applications, such as graphene spin-logic devices, spin memory, and spin torque oscillators. Addressing these challenges in large-scale graphene production can not only resolve fundamental issues but also pave the way for reliable, scalable applications. Chemical vapor deposition (CVD) graphene offers a pathway for efficient charge and spin transport exploration. However, implementing graphene in large-scale electrical circuits remains a core challenge. Specifically, wrinkles and grain boundaries in CVD graphene can affect its electrical quality, and the endurance of electric currents in high-performance devices is a concern. Additionally, commonly used oxide layers such as TiOx and AlOx have unique topographic textures that can induce doping effects in graphene, akin to interactions observed in other 2D materials like MoS2 within heterostructures. This presentation will explore these complex aspects of modifications in graphene's electrical transport in heterostructures and interfaces. Our experiments demonstrate how deposition materials and substrate choice can influence graphene's electrical properties, and how we can use this knowledge to enhance parameters such as carrier doping, mobility, and current sustainability.