Erik Hagersten

Directed Statistical Warming through Time Traveling

Nikoleris, Nikos; Eeckhout, Lieven; Hagersten, Erik; Carlson, Trevor E.

Part of MICRO'52, p. 1037-1049, 2019

DOI for Directed Statistical Warming through Time Traveling

Tail-PASS: Resource-based Cache Management for Tiled Graphics Rendering Hardware

Ceballos, Germán; Hagersten, Erik; Black-Schaffer, David

Part of Proc. 16th International Conference on Parallel and Distributed Processing with Applications, p. 55-63, 2018

DOI for Tail-PASS: Resource-based Cache Management for Tiled Graphics Rendering Hardware

A split cache hierarchy for enabling data-oriented optimizations

Sembrant, Andreas; Hagersten, Erik; Black-Schaffer, David

Part of Proc. 23rd International Symposium on High Performance Computer Architecture, p. 133-144, 2017

DOI for A split cache hierarchy for enabling data-oriented optimizations

Understanding the interplay between task scheduling, memory and performance

Ceballos, Germán; Hagersten, Erik; Black-Schaffer, David

Part of Proc. Companion 8th ACM International Conference on Systems, Programming, Languages, and Applications, p. 21-23, 2017

DOI for Understanding the interplay between task scheduling, memory and performance

A graphics tracing framework for exploring CPU+GPU memory systems

Sembrant, Andreas; Carlson, Trevor E.; Hagersten, Erik; Black-Schaffer, David

Part of Proc. 20th International Symposium on Workload Characterization, p. 54-65, 2017

DOI for A graphics tracing framework for exploring CPU+GPU memory systems

POSTER: Putting the G back into GPU/CPU Systems Research

Sembrant, Andreas; Carlson, Trevor E.; Hagersten, Erik; Black-Schaffer, David

Part of 2017 26TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT), p. 130-131, 2017

DOI for POSTER: Putting the G back into GPU/CPU Systems Research

Approximation: A New Paradigm also for Wireless Sensing

Voigt, Thiemo; Själander, Magnus; Hermans, Frederik; Jimborean, Alexandra et al.

2016

CoolSim: Statistical Techniques to Replace Cache Warming with Efficient, Virtualized Profiling

Nikoleris, Nikos; Sandberg, Andreas; Hagersten, Erik; Carlson, Trevor E.

Part of Proceedings Of 2016 International Conference On Embedded Computer Systems, p. 106-115, 2016

Formalizing data locality in task parallel applications

Ceballos, Germán; Hagersten, Erik; Black-Schaffer, David

Part of Algorithms and Architectures for Parallel Processing, p. 43-61, 2016

DOI for Formalizing data locality in task parallel applications

CoolSim: Eliminating Traditional Cache Warming with Fast, Virtualized Profiling

Nikoleris, Nikos; Sandberg, Andreas; Hagersten, Erik; Carlson, Trevor E.

Part of 2016 IEEE International Symposium On Performance Analysis Of Systems And Software ISPASS 2016, p. 149-150, 2016

Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement

Sembrant, Andreas; Hagersten, Erik; Black-Schaffer, David

Part of Proc. 34th International Conference on Computer Design, p. 117-124, 2016

DOI for Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement

Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors

Sembrant, Andreas; Carlson, Trevor E.; Hagersten, Erik; Black-Schaffer, David et al.

Part of Proc. 48th International Symposium on Microarchitecture, p. 334-346, 2015

DOI for Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors

Effects of Granularity/Adaptivity on Private/Shared Classification for Coherence

Davari, Mahdad; Ros, Alberto; Hagersten, Erik; Kaxiras, Stefanos

2015

StatTask: Reuse distance analysis for task-based applications

Ceballos, Germán; Hagersten, Erik; Black-Schaffer, David

Part of Proc. 7th Workshop on Rapid Simulation and Performance Evaluation, p. 1-7, 2015

DOI for StatTask: Reuse distance analysis for task-based applications

Full speed ahead: Detailed architectural simulation at near-native speed

Sandberg, Andreas; Nikoleris, Nikos; Carlson, Trevor E.; Hagersten, Erik et al.

Part of Proc. 18th International Symposium on Workload Characterization, p. 183-192, 2015

DOI for Full speed ahead: Detailed architectural simulation at near-native speed

Micro-Architecture Independent Analytical Processor Performance and Power Modeling

Van den Steen, Sam; De Pestel, Sander; Mechri, Moncef; Eyerman, Stijn et al.

Part of 2015 IEEE International Symposium on Performance Analysis and Software (ISPASS), p. 32-41, 2015

AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance

Khan, Muneeb; Laurenzano, Michael A.; Mars, Jason; Hagersten, Erik et al.

Part of Proc. 24th International Conference on Parallel Architectures and Compilation Techniques, p. 367-378, 2015

An efficient, self-contained, on-chip directory: DIR₁-SISD

Davari, Mahdad; Ros, Alberto; Hagersten, Erik; Kaxiras, Stefanos

Part of Proc. 24th International Conference on Parallel Architectures and Compilation Techniques, p. 317-330, 2015

DOI for An efficient, self-contained, on-chip directory: DIR₁-SISD

Cost-effective speculative scheduling in high performance processors

Perais, Arthur; Seznec, André; Michaud, Pierre; Sembrant, Andreas et al.

Part of Proc. 42nd International Symposium on Computer Architecture, p. 247-259, 2015

DOI for Cost-effective speculative scheduling in high performance processors

Extending statistical cache models to support detailed pipeline simulators

Nikoleris, Nikos; Eklöv, David; Hagersten, Erik

Part of 2014 IEEE International Symposium On Performance Analysis Of Systems And Software (Ispass), p. 86-95, 2014

DOI for Extending statistical cache models to support detailed pipeline simulators

A software based profiling method for obtaining speedup stacks on commodity multi-cores

Eklöv, David; Nikoleris, Nikos; Hagersten, Erik

Part of 2014 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS), p. 148-157, 2014

DOI for A software based profiling method for obtaining speedup stacks on commodity multi-cores

A case for resource efficient prefetching in multicores

Khan, Muneeb; Sandberg, Andreas; Hagersten, Erik

Part of Proc. International Symposium on Performance Analysis of Systems and Software, p. 137-138, 2014

DOI for A case for resource efficient prefetching in multicores

A case for resource efficient prefetching in multicores

Khan, Muneeb; Sandberg, Andreas; Hagersten, Erik

Part of Proc. 43rd International Conference on Parallel Processing, p. 101-110, 2014

DOI for A case for resource efficient prefetching in multicores

The Direct-to-Data (D2D) Cache: Navigating the cache hierarchy with a single lookup

Sembrant, Andreas; Hagersten, Erik; Black-Schaffer, David

Part of Proc. 41st International Symposium on Computer Architecture, p. 133-144, 2014

DOI for The Direct-to-Data (D2D) Cache: Navigating the cache hierarchy with a single lookup

Resource conscious prefetching for irregular applications in multicores

Khan, Muneeb; Hagersten, Erik

Part of Proc. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), p. 34-43, 2014

DOI for Resource conscious prefetching for irregular applications in multicores

The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence

Davari, Mahdad; Ros, Alberto; Hagersten, Erik; Kaxiras, Stefanos

2014

Bandwidth Bandit: Quantitative Characterization of Memory Contention

Eklöv, David; Nikoleris, Nikos; Black-Schaffer, David; Hagersten, Erik

Part of Proc. 11th International Symposium on Code Generation and Optimization, p. 99-108, 2013

DOI for Bandwidth Bandit: Quantitative Characterization of Memory Contention

TLC: A tag-less cache for reducing dynamic first level cache energy

Sembrant, Andreas; Hagersten, Erik; Black-Schaffer, David

Part of Proceedings of the 46th International Symposium on Microarchitecture, p. 49-61, 2013

DOI for TLC: A tag-less cache for reducing dynamic first level cache energy

Modeling performance variation due to cache sharing

Sandberg, Andreas; Sembrant, Andreas; Hagersten, Erik; Black-Schaffer, David

Part of Proc. 19th IEEE International Symposium on High Performance Computer Architecture, p. 155-166, 2013

Low Overhead Instruction-Cache Modeling Using Instruction Reuse Profiles

Khan, Muneeb; Sembrant, Andreas; Hagersten, Erik

Part of International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'12), p. 260-269, 2012

DOI for Low Overhead Instruction-Cache Modeling Using Instruction Reuse Profiles

Phase Guided Profiling for Fast Cache Modeling

Sembrant, Andreas; Black-Schaffer, David; Hagersten, Erik

Part of International Symposium on Code Generation and Optimization (CGO'12), p. 175-185, 2012

DOI for Phase Guided Profiling for Fast Cache Modeling

Phase Behavior in Serial and Parallel Applications

Sembrant, Andreas; Black-Schaffer, David; Hagersten, Erik

Part of International Symposium on Workload Characterization (IISWC'12), 2012

Efficient techniques for predicting cache sharing and throughput

Sandberg, Andreas; Black-Schaffer, David; Hagersten, Erik

Part of Proc. 21st International Conference on Parallel Architectures and Compilation Techniques, p. 305-314, 2012

Bandwidth bandit: Quantitative characterization of memory contention

Eklöv, David; Nikoleris, Nikkos; Black-Schaffer, David; Hägersten, Erik

Part of Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, p. 457-458, 2012

DOI for Bandwidth bandit: Quantitative characterization of memory contention

Cache Pirating: Measuring the Curse of the Shared Cache

Eklöv, David; Nikoleris, Nikos; Black-Schaffer, David; Hagersten, Erik

Part of Proc. 40th International Conference on Parallel Processing, p. 165-175, 2011

DOI for Cache Pirating: Measuring the Curse of the Shared Cache

Fast modeling of shared caches in multicore systems

Eklöv, David; Black-Schaffer, David; Hagersten, Erik

Part of Proc. 6th International Conference on High Performance and Embedded Architectures and Compilers, p. 147-157, 2011

DOI for Fast modeling of shared caches in multicore systems

A simple statistical cache sharing model for multicores

Sandberg, Andreas; Black-Schaffer, David; Erik, Hagersten

Part of Proc. 4th Swedish Workshop on Multi-Core Computing, p. 31-36, 2011

Download full text (pdf) of A simple statistical cache sharing model for multicores

Efficient software-based online phase classification

Sembrant, Andreas; Eklöv, David; Hagersten, Erik

Part of International Symposium on Workload Characterization (IISWC'11), p. 104-115, 2011

DOI for Efficient software-based online phase classification

StatStack: Efficient modeling of LRU caches

Eklöv, David; Hagersten, Erik

Part of Proc. International Symposium on Performance Analysis of Systems and Software, p. 55-65, 2010

DOI for StatStack: Efficient modeling of LRU caches

Reducing Cache Pollution Through Detection and Elimination of Non-Temporal Memory Accesses

Sandberg, Andreas; Eklöv, David; Hagersten, Erik

Part of Proc. International Conference for High Performance Computing, Networking, Storage and Analysis, p. 11, 2010

StatCC: a statistical cache contention model

Eklöv, David; Black-Schaffer, David; Hagersten, Erik

Part of Proc. 19th International Conference on Parallel Architectures and Compilation Techniques, p. 551-552, 2010

DOI for StatCC: a statistical cache contention model

A Software Technique for Reducing Cache Pollution

Sandberg, Andreas; Eklöv, David; Hagersten, Erik

Part of Proc. 3rd Swedish Workshop on Multi-Core Computing, p. 59-62, 2010

Download full text (pdf) of A Software Technique for Reducing Cache Pollution

Improving cache utilization using Acumem VPE

Hagersten, Erik; Nilsson, Mats; Vesterlund, Magnus

Part of Tools for High Performance Computing, p. 115-135, 2008

DOI for Improving cache utilization using Acumem VPE

Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution.

Karlsson, Martin; Hagersten, Erik

Part of 21st International Parallel and Distributed Processing Symposium, 2007

A case for low-complexity MP architectures

Zeffer, Håkan; Hagersten, Erik

Part of Proc. Conference on Supercomputing, p. 559-570, 2007

DOI for A case for low-complexity MP architectures

A Statistical Multiprocessor Cache Model

Berg, Erik; Zeffer, Håkan; Hagersten, Erik

Part of Proc. International Symposium on Performance Analysis of Systems and Software, p. 89-99, 2006

DOI for A Statistical Multiprocessor Cache Model

Modeling cache sharing on chip multiprocessor architectures

Petoumenos, Pavlos; Keramidas, Georgios; Zeffer, Håkan; Kaxiras, Stefanos et al.

Part of Proc. International Symposium on Workload Characterization, p. 160-171, 2006

DOI for Modeling cache sharing on chip multiprocessor architectures

Multigrid and Gauss-Seidel smoothers revisited: Parallelization on chip multiprocessors

Wallin, Dan; Löf, Henrik; Hagersten, Erik; Holmgren, Sverker

Part of Proc. 20th ACM International Conference on Supercomputing, p. 145-155, 2006

DOI for Multigrid and Gauss-Seidel smoothers revisited: Parallelization on chip multiprocessors

Exploiting Locality: A Flexible DSM Approach

Zeffer, Håkan; Radović, Zoran; Hagersten, Erik

Part of Proc. 20th IEEE International Parallel and Distributed Processing Symposium, 2006

TMA: A Trap-based Memory Architecture

Zeffer, Håkan; Radović, Zoran; Karlsson, Martin; Hagersten, Erik

Part of Proc. 20th ACM International Conference on Supercomputing, p. 259-268, 2006

Vasa: A Simulator Infrastructure with Adjustable Fidelity

Wallin, Dan; Zeffer, Håkan; Karlsson, Martin; Hagersten, Erik

Part of In Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2005), Phoenix, Arizona, USA, November 2005., 2005

Exploring Processor Design Options for Java Based Middleware

Karlsson, Martin; Moore, Kevin; Hagersten, Erik; Wood, David

Part of Proceedings of the 2005 International Conference on Parallel Processing (ICPP-05), 2005

Skewed Caches from a Low-Power Perspective

Spjuth, Mathias; Karlsson, Martin; Hagersten, Erik

Part of Proceedings of Computing Frontiers, Ischia, Italy, May 2005, 2005

Exploiting Spatial Store Locality through Permission Caching in Software DSMs

Zeffer, Håkan; Radovic, Zoran; Grenholm, Oskar; Hagersten, Erik

Part of Proceedings of the 10th International Euro-Par Conference, p. 551, 2004

Bundling: Reducing the Overhead of Multiprocessor Prefetchers

Wallin, Dan; Hagersten, Erik

Part of 18th International Parallel and Distributed Processing Symposium, 2004

StatCache: A Probabilistic Approach to Efficient and Accurate Data Locality Analysis

Berg, Erik; Hagersten, Erik

Part of 2004 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2004),, 2004

Hierarchical Backoff Locks for Nonuniform Communication Architectures

Radovic, Zoran; Hagersten, Erik

Part of Proceedings of the Ninth International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, California, USA, February 2003., 2003

THROOM — Supporting POSIX Multithreaded Binaries on a Cluster

Löf, Henrik; Radović, Zoran; Hagersten, Erik

Part of Euro-Par 2003, p. 760-769, 2003

DOI for THROOM — Supporting POSIX Multithreaded Binaries on a Cluster

Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors

Wallin, Dan; Hagersten, Erik

Part of Proceedings of the 17th InternationalParallel and Distributed Processing Symposium (IPDPS 2003), Nice, France, 2003

Memory System Behavior of Java-Based Middleware

Karlsson, Martin; Moore, Kevin; Hagersten, Erik; Wood, David

Part of Proceedings of the Ninth International Symposium on High Performance Computer Architecture, 2003

RH Lock: A Scalable Hierarchical Spin Lock

Radovic, Zoran; Hagersten, Erik

Part of Proceedings of the 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), held in conjunction with the 29th International Symposium on Computer Architecture (ISCA29), Anchorage, Alaska, USA, 2002

Efficient Synchronization for Non-Uniform Communication Architectures

Radovic, Zoran; Hagersten, Erik

Part of Proceedings of Supercomputing 2002, Baltimore, Maryland, USA, 2002

WildFire: A Scalable Path for SMPs

Hagersten, Erik; Koster, Michael

Part of Proc. Fifth Int. Symp. on High-Performance Computer Architecture, p. 172-181, 1999

DOI for WildFire: A Scalable Path for SMPs

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