Computer Architecture I
Syllabus, Bachelor's level, 1DT038
- Education cycle
- First cycle
- Main field(s) of study and in-depth level
- Computer Science G1F, Technology G1F
- Grading system
- Fail (U), Pass (3), Pass with credit (4), Pass with distinction (5)
- Finalised by
- The Faculty Board of Science and Technology, 12 April 2016
- Responsible department
- Department of Information Technology
Computer Programming II.
Upon successful completion of the course, the students should be able to:
- Describe the operation of a computer processor, including its control logic, processor pipelining, I/O system, and memory system.
- Implement basic pipelined and non-pipelined processors from logic gates.
- Analyse the performance trade-offs in the ISA, processor, memory system, and I/O interfaces.
- Write and debug elementary programs in assembly language.
The von Neumann. RISC architectures; instruction encoding, decoding and execution; Instruction set architecture (ISA) design; processor control and datapath implementation; pipelining; hazards; branch prediction; caches; virtual memory; I/O; basic parallelism; and assembly programming.
Lectures, seminars, and assignments.
Written exam (2 hp). Written and oral examination of assignments and labs.