Digital Electronics Design with VHDL

10 credits

Syllabus, Master's level, 1FA326

A revised version of the syllabus is available.
Code
1FA326
Education cycle
Second cycle
Main field(s) of study and in-depth level
Embedded Systems A1N, Technology A1N
Grading system
Pass with distinction (5), Pass with credit (4), Pass (3), Fail (U)
Finalised by
The Faculty Board of Science and Technology, 14 February 2017
Responsible department
Department of Physics and Astronomy

Entry requirements

120 credits in technology/science including basic course in digital electronics (especially state machines), for example Electronics I, and programming.

Learning outcomes

On completion of the course, the student should be able to:

  • account for the syntax and behaviour of the VHDL language
  • use modern development tools to design complex digital circuits
  • simulate and make a synthesis of extensive designs in so called "Field Programmable Gate Array" (FPGA:er).

Content

Introduction: Overview of different design styles and abstraction methods.

VHDL: The program language aspects for modelling and specification. The abstraction levels of the VHDL language. Components. Instantiation. Parallel expressions (if, case wait and loops). Functions and Procedures.

Design tools: From simple VHDL editors to graphical editors, simulators and tools for synthesis of VHDL descriptions for FPGA circuits.

Laboratory work: Related to basic components that are used for example in so called embedded systems.

Projects: A relatively extensive project in simulation and synthesis to achieve a non-trivial (industry relevant) design in a FPGA.

How completed design blocks (so called IPs) can be used to achieve extensive circuit solutions in FPGAs and how to put together a so-called System On a Programmable Chip where an advanced processor is put together and is tested using the C programming language.

Instruction

Lectures, lab-exercises and a project.

Assessment

Project Work with report and individual review in examination form . Active participation during the scheduled hours. Optional written examination.

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