Syllabus for Computer Architecture I

Datorarkitektur I

A revised version of the syllabus is available.

Syllabus

  • 5 credits
  • Course code: 1DT038
  • Education cycle: First cycle
  • Main field(s) of study and in-depth level: Computer Science G1F, Technology G1F

    Explanation of codes

    The code indicates the education cycle and in-depth level of the course in relation to other courses within the same main field of study according to the requirements for general degrees:

    First cycle

    • G1N: has only upper-secondary level entry requirements
    • G1F: has less than 60 credits in first-cycle course/s as entry requirements
    • G1E: contains specially designed degree project for Higher Education Diploma
    • G2F: has at least 60 credits in first-cycle course/s as entry requirements
    • G2E: has at least 60 credits in first-cycle course/s as entry requirements, contains degree project for Bachelor of Arts/Bachelor of Science
    • GXX: in-depth level of the course cannot be classified

    Second cycle

    • A1N: has only first-cycle course/s as entry requirements
    • A1F: has second-cycle course/s as entry requirements
    • A1E: contains degree project for Master of Arts/Master of Science (60 credits)
    • A2E: contains degree project for Master of Arts/Master of Science (120 credits)
    • AXX: in-depth level of the course cannot be classified

  • Grading system: Fail (U), Pass (3), Pass with credit (4), Pass with distinction (5)
  • Established: 2008-03-18
  • Established by:
  • Revised: 2018-08-30
  • Revised by: The Faculty Board of Science and Technology
  • Applies from: Autumn 2019
  • Entry requirements:

    Computer Programming II.

  • Responsible department: Department of Information Technology

Learning outcomes

On completion of the course, the student should be able to:

  • Describe the operation of a computer processor, including its control logic, processor pipelining, I/O system, and memory system.
  • Implement basic pipelined and non-pipelined processors from logic gates.
  • Analyse the performance trade-offs in the ISA, processor, memory system, and I/O interfaces.
  • Write and debug elementary programs in assembly language.

Content

The von Neumann. RISC architectures; instruction encoding, decoding and execution; Instruction set architecture (ISA) design; processor control and datapath implementation; pipelining; hazards; branch prediction; caches; virtual memory; I/O; basic parallelism; and assembly programming.

Instruction

Lectures, seminars, and assignments.

Assessment

Written exam (2 hp). Written and oral examination of assignments and labs.

If there are special reasons for doing so, an examiner may make an exception from the method of assessment indicated and allow a student to be assessed by another method. An example of special reasons might be a certificate regarding special pedagogical support from the disability coordinator of the university.

Syllabus Revisions

Reading list

Reading list

Applies from: Autumn 2019

Some titles may be available electronically through the University library.

  • Patterson, David A.; Hennessy, John L. Computer organization and design : the hardware/software interface

    4. ed.: Amsterdam: Elsevier Morgan Kaufmann, cop. 2009

    Find in the library

Print syllabus and reading list
Print