Computer Architecture I
Syllabus, Bachelor's level, 1DT038
- Code
- 1DT038
- Education cycle
- First cycle
- Main field(s) of study and in-depth level
- Computer Science G1F, Technology G1F
- Grading system
- Fail (U), Pass (3), Pass with credit (4), Pass with distinction (5)
- Finalised by
- The Faculty Board of Science and Technology, 30 August 2018
- Responsible department
- Department of Information Technology
Entry requirements
Computer Programming II.
Learning outcomes
On completion of the course, the student should be able to:
- Describe the operation of a computer processor, including its control logic, processor pipelining, I/O system, and memory system.
- Implement basic pipelined and non-pipelined processors from logic gates.
- Analyse the performance trade-offs in the ISA, processor, memory system, and I/O interfaces.
- Write and debug elementary programs in assembly language.
Content
The von Neumann. RISC architectures; instruction encoding, decoding and execution; Instruction set architecture (ISA) design; processor control and datapath implementation; pipelining; hazards; branch prediction; caches; virtual memory; I/O; basic parallelism; and assembly programming.
Instruction
Lectures, seminars, and assignments.
Assessment
Written exam (2 hp). Written and oral examination of assignments and labs.
If there are special reasons for doing so, an examiner may make an exception from the method of assessment indicated and allow a student to be assessed by another method. An example of special reasons might be a certificate regarding special pedagogical support from the disability coordinator of the university.