Accelerating Systems with Programmable Logic Components

10 credits

Course, Master's level, 1DT109

Expand the information below to show details on how to apply and entry requirements.

Location
Uppsala
Pace of study
33%
Teaching form
On-campus
Instructional time
Daytime
Study period
1 September 2025–18 January 2026
Language of instruction
English
Entry requirements

120 credits including Computer Architecture, a basic course in digital circuits (especially state machines) and a basic course in programming. Proficiency in English equivalent to the Swedish upper secondary course English 6.

Selection

Higher education credits in science and engineering (maximum 240 credits)

Fees
If you are not a citizen of a European Union (EU) or European Economic Area (EEA) country, or Switzerland, you are required to pay application and tuition fees.
  • First tuition fee instalment: SEK 24,167
  • Total tuition fee: SEK 24,167

Read more about fees.

Application deadline
15 April 2025
Application code
UU-11201

Admitted or on the waiting list?

Registration period
25 July 2025–7 September 2025
Information on registration from the department

Location
Uppsala
Pace of study
33%
Teaching form
On-campus
Instructional time
Daytime
Study period
1 September 2025–18 January 2026
Language of instruction
English
Entry requirements

120 credits including Computer Architecture, a basic course in digital circuits (especially state machines) and a basic course in programming. Proficiency in English equivalent to the Swedish upper secondary course English 6.

Admitted or on the waiting list?

Registration period
25 July 2025–7 September 2025
Information on registration from the department

About the course

On completion of the course, you should be able to:

  • define complex digital circuits using hardware description languages such as VHDL or Verilog
  • test, debug, and verify digital designs using test benches and simulation tools
  • integrate custom programmable logic components with processor-based systems
  • analyse power and performance of accelerating key system components
  • demonstrate how a processor interacts with an accelerator through software

Content:

  • Syntax and semantics of hardware description languages, and their use to define digital systems.
  • Design and implementation of test benches and the use of simulation-based and on-chip debugging facilities for verifying system designs.
  • Parallelisation of key algorithms for higher throughput and lower latency.
  • Integration of hardware accelerators at the system- and software levels.
  • Overview of different design styles and abstraction methods.
  • An extensive project in simulation and synthesis, designing a realistic accelerator for a system-on-chip processor system.

No reading list found.

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