Yuan Yao

Biografi

2009 fick jag kandidatexamen med inriktning mot mikroelektronik på Northwestern Polytechnical University i Kina. 2014 fick jag masterexamen med inriktning mot systemkonstruktion på kisel på Kungliga Tekniska Högskolan i Sverige. Jag är doktorand på skolan för elektroteknik och datavetenskap (EECS) vid KTH, 2015-2019.

Forskning

Research Interests:

• Computer architecture design, power and thermal control for chip multi-/many-processors (CMPs), Network-on-Chips (NoCs), and GPGPUs.
• Coherency/consistency provisioning for emerging memory techniques.
• Hardware/Software co-design for high performance parallel computing architectures.
• Performance analysis and QoS for on-chip networking and memory systems.

Publications

Conference paper

1. Yuan Yao and Zhonghai Lu, “iNPG: Accelerating Critical Section Access with InNetwork Packet Generation for NoC Based Many-Cores”, in Proceedings of the 24nd IEEE International Symposium on High Performance Computer Architecture (HPCA, *Best paper candidate*), Vienna, Feb. 2018.

2. Yuan Yao and Zhonghai Lu, “Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC based CMPs”, in Proceedings of the 43rd International Symposium on Computer Architecture (ISCA), Seoul, Jul. 2016.

3. Yuan Yao and Zhonghai Lu, “Memory-Access Aware DVFS for Network-onChip in CMPs”, in Proceedings of Design, Automation & Test in Europe (DATE), Dresden, Mar. 2016.

4. Yuan Yao and Zhonghai Lu, “DVFS for NoCs in CMPs: A Thread Voting Approach”, in Proceedings of the 22nd IEEE International Symposium on High Performance Computer Architecture (HPCA), Barcelona, Feb. 2016.

5. Zhonghai Lu, Yuan Yao, Yuming Jiang, “Towards Stochastic Delay Bound Analysis for Network-on-Chip”, in IEEE/ACM International Symposium on Networkon-Chip (NoCS), Ferrere, Sep. 2014.

6. Yuan Yao and Zhonghai Lu, “Fuzzy Flow Regulation for Network-on-Chip based Chip Multiprocessors Systems”, in 19th Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, Feb. 2014.

Journal paper

1. Yuan Yao and Zhonghai Lu, “Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS”, in IEEE Transactions on Computers (TC, Volume: 69, Issue: 3), Mar. 2020.

2. Zhonghai Lu and Yuan Yao, “Thread Voting DVFS for Manycore NoCs”, in IEEE Transactions on Computers (TC, Volume: 67, Issue: 10), Oct. 2018.

3. Zhonghai Lu and Yuan Yao, “Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS”, in IEEE Transactions on Computers (TC, Volume: 66, Issue: 11), Nov. 2017.

4. Zhonghai Lu and Yuan Yao, “Dynamic Traffic Regulation in NoC-Based Systems”, in IEEE Transactions on Very Large Scale Integration Systems (TVLSI, Volume: 25, Issue: 2), Feb. 2017.

5. Zhonghai Lu and Yuan Yao, “Aggregate Flow-Based Performance Fairness in CMPs”, in ACM Transactions on Architecture and Code Optimization (TACO, Volume 13 Issue 4), Dec. 2016.

Work-in-progress

1. Yuan Yao and Zhonghai Lu, "Work-in-progress: Prediction based Convolution Neural Network Acceleration", in International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Oct. 2017.

Media

My personal websize

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https://winternan.github.io