Chang Hyun Park
Biträdande universitetslektor vid Institutionen för informationsteknologi; Datorteknik
- Telefon:
- 018-471 29 73
- E-post:
- chang.hyun.park@it.uu.se
- Besöksadress:
- Hus 10, Regementsvägen 10
- Postadress:
- Box 337
751 05 UPPSALA
- ORCID:
- 0000-0002-8250-8574

Publikationer
Senaste publikationer
Accelerating Page Migrations in Operating Systems with Intel DSA
Ingår i IEEE Computer Architecture Letters, s. 37-40, 2025
Ingår i The International Symposium on Memory Systems (MEMSYS '23), s. 1-11, 2023
- DOI för Large-scale Graph Processing on Commodity Systems: Understanding and Mitigating the Impact of Swapping
- Ladda ner fulltext (pdf) av Large-scale Graph Processing on Commodity Systems: Understanding and Mitigating the Impact of Swapping
Protean: Resource-efficient Instruction Prefetching
Ingår i The International Symposium on Memory Systems (MEMSYS '23), s. 1-13, 2023
- DOI för Protean: Resource-efficient Instruction Prefetching
- Ladda ner fulltext (pdf) av Protean: Resource-efficient Instruction Prefetching
Exploring the Latency Sensitivity of Cache Replacement Policies
Ingår i IEEE Computer Architecture Letters, s. 93-96, 2023
- DOI för Exploring the Latency Sensitivity of Cache Replacement Policies
- Ladda ner fulltext (pdf) av Exploring the Latency Sensitivity of Cache Replacement Policies
Every Walk's a Hit: Making Page Walks Single-Access Cache Hits
Ingår i Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’22), February 28 – March 4, 2022, Lausanne, Switzerland, 2022
- DOI för Every Walk's a Hit: Making Page Walks Single-Access Cache Hits
- Ladda ner fulltext 1 (pdf) av Every Walk's a Hit: Making Page Walks Single-Access Cache Hits
- Ladda ner fulltext 2 (pdf) av Every Walk's a Hit: Making Page Walks Single-Access Cache Hits
Alla publikationer
Artiklar i tidskrift
Accelerating Page Migrations in Operating Systems with Intel DSA
Ingår i IEEE Computer Architecture Letters, s. 37-40, 2025
Exploring the Latency Sensitivity of Cache Replacement Policies
Ingår i IEEE Computer Architecture Letters, s. 93-96, 2023
- DOI för Exploring the Latency Sensitivity of Cache Replacement Policies
- Ladda ner fulltext (pdf) av Exploring the Latency Sensitivity of Cache Replacement Policies
A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006
Ingår i ACM Transactions on Architecture and Code Optimization (TACO), 2021
Reconciling Time Slice Conflicts of Virtual Machines With Dual Time Slice for Clouds
Ingår i IEEE Transactions on Parallel and Distributed Systems, s. 2453-2465, 2020
Dataset
Konferensbidrag
Ingår i The International Symposium on Memory Systems (MEMSYS '23), s. 1-11, 2023
- DOI för Large-scale Graph Processing on Commodity Systems: Understanding and Mitigating the Impact of Swapping
- Ladda ner fulltext (pdf) av Large-scale Graph Processing on Commodity Systems: Understanding and Mitigating the Impact of Swapping
Protean: Resource-efficient Instruction Prefetching
Ingår i The International Symposium on Memory Systems (MEMSYS '23), s. 1-13, 2023
- DOI för Protean: Resource-efficient Instruction Prefetching
- Ladda ner fulltext (pdf) av Protean: Resource-efficient Instruction Prefetching
Every Walk's a Hit: Making Page Walks Single-Access Cache Hits
Ingår i Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’22), February 28 – March 4, 2022, Lausanne, Switzerland, 2022
- DOI för Every Walk's a Hit: Making Page Walks Single-Access Cache Hits
- Ladda ner fulltext 1 (pdf) av Every Walk's a Hit: Making Page Walks Single-Access Cache Hits
- Ladda ner fulltext 2 (pdf) av Every Walk's a Hit: Making Page Walks Single-Access Cache Hits
Supporting Dynamic Translation Granularity for Hybrid Memory Systems
Ingår i 2022 IEEE 40th International Conference on Computer Design (ICCD), s. 25-32, 2022
Architecturally-independent and time-based characterization of SPEC CPU 2017
Ingår i 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), s. 107-109, 2020
- DOI för Architecturally-independent and time-based characterization of SPEC CPU 2017
- Ladda ner fulltext 1 (pdf) av Architecturally-independent and time-based characterization of SPEC CPU 2017
- Ladda ner fulltext 2 (pdf) av Architecturally-independent and time-based characterization of SPEC CPU 2017
Perforated Page: Supporting Fragmented Memory Allocation for Large Pages
Ingår i Proceedings of the 47th Annual ACM/IEEE International Symposium on Computer Architecture (ISCA), s. 913-925, 2020
- DOI för Perforated Page: Supporting Fragmented Memory Allocation for Large Pages
- Ladda ner fulltext (pdf) av Perforated Page: Supporting Fragmented Memory Allocation for Large Pages
Decoupled Address Translation for Heterogeneous Memory Systems
Ingår i PACT '20, s. 155-156, 2020